Sonifex Software
RB-VHDMA8, RB-VHEMA8, RB-VHCMA4 & RB-VHCMD16 Firmware Versions
FPGA V0.2.7
- Fixed audio routing error introduced in version 0.2.6.
FW V0.3.1 / FPGA V0.2.6
- Firmware
- Reverted default IP address back to 192.168.0.100 and gateway to 192.168.0.1 to remain standard with other units
- FPGA
- Fixed bug where HD Luma/Chroma streams would sometimes become misaligned during locking.
FPGA V0.2.4/5
- Internal versions. Not released.
FW V0.3.0 / FPGA V0.2.3
- Firmware
- Now allows multiple connections over TCP/IP.
- New command RWC; Requests write permission (RS-232 always has write permission).
- New command WAL; Changes "login" details for write permission.
- New command GAC; Retrieves current "admin" connection(s).
- Updated TCP/IP stack.
- Improved message handling from UART, TCP and UDP connections.
- Changed default IP address to 192.168.1.2 and gateway to 192.168.1.1.
- Changed command CLR; Resets login details to defaults.
- Can no longer press+hold the bank channel button while in bank mode.
- Improved FPGA/firmware update process.
- Channel status is no longer continously read/written when digital I/O sub-boards are fitted. Changes in the data are detected and written in a round robin sequence.
- Other minor improvements.
- FPGA
- Channel status for channels 2 and 4 in a group are now de-embedded correctly into RAM.
FW V0.2.1 / FPGA V0.2.2
- FPGA
- Corrected clock phase information for HD audio packets.
V0.2.1/V0.2.1
- FPGA
- Corrected parity bit in SD audio packets.
V0.2.1/V0.2.0
- Firmware
- Rebuild for new CPU soft core, with updated drivers.
- SDI locking improved.
- Fixed SCId memory leak.
- Other minor changes/fixes.
- FPGA
- Corrected data block numbering in audio packets.
- New CPU soft core version.
- SDI locking improved.
V0.1.8/V0.1.1
- Initial release
